This invention relates to multiprocessor computer systems and more particularly, to such a system including a plurality of tightly coupled processors.
Current developments in the computer industry have caused an ever increasing trend towards larger and more sophisticated computing systems. These developments have in many cases been made possible by higher speed and less expensive circuit elements. Further increases in system throughput have come from improved organization of the computing systems. Of particular note in terms of organization is the multiprocessor computing systems wherein several autonomous processing units are capable of sharing a common workload.
Over the years many different types of multiprocessor configurations have been designed. In fact, many mainframe vendors and some minicomputer suppliers currently offer systems with two to four processors. To date, these structures have been expensive to build due to the high cost of the typical processors. Therefore, multiprocessor computer systems have found application mostly for high-availability computing (e.g., communications, banking, airline reservations).
Another purpose of providing multiprocessor arrangements is to increase computational power and speed by employing a plurality of processing units which operate in parallel so as to obtain a data throughput greater than that achievable by a single processor operating at any achievable speed. Many algorithms and computations typically handled by digital computers can be parallel processed. Further, since the cost of increasing processor speed increases sharply beyond a predetermined point, it can be shown that throughput above a corresponding level can be achieved more economically by employing a greater number of relatively slow processors than by increasing the speed of a single processor. In view of the rapid rate of microprocessor evolution, the number of sensitive applications requiring single-stream performance in excess of that delivered by a single processor is already quite small and will continue to shrink.
Some of the advantages gained through the use of multiprocessors are achieved at the expense of incurring considerable penalty in terms of system reliability and increased difficulty in programming. The shortcomings are typically due to hierarchical organization of the processors. One characteristic often contributing to reliability problems was the usual organizational arrangement where each communications or input/output device was associated with a given one of the processors. A failure in that one processor would cause the entire system to be unable to fulfill its overall intended purpose.
Typical multiprocessor systems are coupled in one of two ways. In a "closely-coupled" multiprocessor system, each processor runs in a closed computing environment consisting of a processor, a private memory, an I/O interface, and a separate operating system. Flexibility and power are restricted in such a system because each processor is as isolated as it would be if it were an independent system in a fast network. In addition, more than one processor cannot efficiently be applied to the same task without large amounts of data and context being transferred each time a switch is made. Thus a limit is placed on how dynamically the pool of processors can be balanced to a quickly changing task load.
In a tightly coupled system, multiprocessors share a common bus, memory, input/output devices and an operating system. In such an architecture, only one copy of the operating system is needed for hundreds of processes running on a large number of individual microprocessors. All processors--and processes--share access to all of main memory, all network and I/O interfaces, and all of mass storage. This sharing allows maximum utilization of available processors with minimum waste of memory space and bus bandwidth because shared access requires minimum copying of data and minimum context switching. In such a system, any processor can be used at any time for any process. The enormous flexibility of this design pays off in greater available power, greater expansion potential, and a much wider range of applications.
There are various considerations that should be taken into account when designing a multiprocessor system in order to obtain the maximum performance level. One such factor is that a given vendor should provide a fairly large variety of multiprocessor systems. This variety should take into account both performance and price considerations. Having to choose among a limited number of computer family members is often not a satisfactory solution since it is expensive to design and develop different computer family members.
Another important consideration in the design of a multiprocessor computer system is that when the system is designed from a number of different type of modules such as processors, I/O devices, and memory modules, the failure of one such module should not result in failure of the multiprocessor computer system. Ideally, appropriate software support should allow faulty modules to be replicated and taken out of service thereby allowing continuing operation with minimum down time.
In order to keep design costs of a multiprocessor system as low as possible, it is important that the multiprocessor computer system is not comprised of a large number of unique boards in a typical minicomputer. Instead, if the multiprocessor computer system is comprised of multiple copies of a small number of modules the system is faster and less expensive to design, and individual module types can be produced in large volumes, producing improvements in manufacturing costs over older technologies.
In any multiprocessor system in which performance and flexibility are of the utmost importance, the bus which connects the various modules of the system must have a very high data transfer rate. Such a system must also be able to fairly arbitrate access to the bus so that no module is continuously denied access. To achieve a high data transfer rate, it is also generally preferred that the bus be a pended bus, i.e. a bus with a structure which allows requests for information to be disassociated in time from the replies they generate. Pending of operations allows a number of relatively slow devices (e.g. processors) to communicate with other slow devices (e.g. main memory banks) without compromising the bandwidth of a bus designed to accomodate higher speed transfers than any single device can manage by itself. When requests are pended, they are tagged with the requestor's ID and sent to the recipient at the first opportunity. When the recipient replies at some later time, the reply is tagged with the requestor's ID. Neither participant in the transaction is aware that many other transactions involving other requestors and recipients may have intervened between the request and its reply.
In any computer system containing more than one processor there is also the requirement that any processor be able to perform atomic test and set operations on memory. One obvious way to insure atomicity is to tie up the path to memory, i.e., the bus, for an entire read-modify-write operation. In a performance sensitive system, this is clearly undesirable. On a pended bus, i.e., a bus where read cycles are interleaved with other bus operations, the path to memory cannot be tied up. The result is that an external method is required to lock a memory location. Since the memories of the present invention are interleaved on a bank basis, it will be possible to lock memory on a bank by bank basis. Given the size of the memory bank, however, locking memory on four megabyte boundaries is very undesirable.
It is therefore a principle object of the present invention to provide a multiprocessor computer system which includes a large number of processors.
Another object of the present invention is to provide a multiprocessor computer system in which the multiple processors are tightly coupled.
Yet another object of the present invention is to provide a multiprocessor computer system in which a user can construct a correct level of performance or price, without having to choose among a limited number of computer family members.
Still another object of the present invention is to provide a multiprocessor computer system which possesses inherent reliability achieved through the use of a small number of module types which can be taken out of service without affecting the remainder of the system.
A further object of the present invention is to provide a multiprocessor computer system which can transfer vectored interrupts without tying up the data and/or address buses.
A still further object of the present invention is to provide a multiprocessor computer system which includes multiple copies of a small number of modules.
Yet another object of the present invention is to provide a multiprocessor computer system which can be expanded by being interconnected with another similar multiprocessor computer system.
Still another object of the present invention is to provide a multiprocessor computer system which includes a system bus with a very high data transfer speeds.
Another object of the present invention is to provide a multiprocessor computer system which includes a memory system which can perform atomic test and set operations without tying up the system bus.